ASU工程学院IEEE Fellow招24Spring全奖PhD，欢迎投递

基本情况


Professor: Chaitali Chakrabarti, IEEE Fellow, 主要研究方向是software-hardware codesign 特别是低功耗设计。全ECEE最好的老板之一，对学生非常有耐心，每周都会一对一讨论。一般4-5年毕业，全程都有funding。不发水文，不push，不卡实习，不卡毕业。已经毕业的学生大多就职于各互联网或硬件大厂。


Bio
Chaitali Chakrabarti received her B. Tech. in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 1984. She received her M.S. and Ph.D. in Electrical Engineering Dept from U. of Maryland, College Park in 1986 and 1990 respectively. She has been at ASU since fall 1990.
Chaitali's research interests are in the areas of VLSI architectures for signal processing and communications, algorithm-architecture co-design of signal processing systems, and all aspects of low power embedded system design including those that operate at near-threshold voltages. She is an Associate Editor of the Journal of VLSI Signal Processing Systems (1999-present), and on the Senior Editorial Board of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2013-present). She also served as the Associate Editor of IEEE Trans on Signal Processing (1999-2005), IEEE Transactions on VLSI Systems (2007-2013), IEEE Transactions on Multi-scale Computing Systems (2017-2018), and as the Chair of the Technical Committee on Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society, (2006-2007).
Chaitali teaches undergraduate courses on Digital Design Fundamentals, Signals and Systems, Digital Systems and Circuits as well as graduate courses on VLSI Design, and VLSI architectures. She is the recipient of the 1994 CEAS Young Faculty Teaching Excellence award, the 2001 IEEE Phoenix Chapter's Outstanding Educator award, the Top Five Percent Teaching award at the Ira A. Fulton Schools of Engineering Award in 2012, 2014, 2018, 2019, 2020 and 2022, and the Ira A. Fulton Schools of Engineering Exemplar Faculty Award in 2014 and 2015. Chaitali received the 2013 Distinguished ECE Alumni Award from the ECE Department at the University of Maryland, College Park and the 2018 Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. She is also the recipient of the Joseph Palais Distinguished Faculty Scholar Award in 2021. Chaitali is a Fellow of the IEEE.
更多详情请见https://www.public.asu.edu/~chaitali/
欢迎有兴趣的同学请把简历，成绩单以及英语成绩证明发送到xchen382@asu.edu （注明博士申请）条件符合我们会在第一时间安排面试。






职位介绍与要求
Job1: 做 Reconfigurable accelerator 的compiler工作，和组里另一位PhD一起协作完成。
要求：
1）熟悉embedded system 与 FPGA
2)  有research经验
3）熟练的coding能力
4）TOEFL>90和GRE>310，其他英语考试成绩要求可以参考ASU官网。特别优秀的同学我们会帮忙争取降低要求。
加分项：
1）熟悉computer architecture
2）熟悉VLSI deign
3)  对Machine learning有一定了解
4）发表过论文




Job2: Communication/Signal Processing/Reinforcement Learning Software-Hardware Co-design。
要求（以下要求1-3满足任意一条即可）：
1）有communication and signal processing相关背景
2）对hardware有一定了解，比如上过一些单片机，FPGA的课程，学过汇编等等
3）对Reinforcement learning 有了解，或者至少对Machine Learning有了解
3)  有research经验
4）熟练的coding能力
5）TOEFL>90和GRE>310，其他英语考试成绩要求可以参考ASU官网。特别优秀的同学我们会帮忙争取降低要求。
加分项：
1）熟悉computer architecture
2）熟悉VLSI deign
3）发表过论文