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[我司要招人] 高通SD组内招Timing and Technology Engineer

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2024(4-6月)-EE本科+1-3年 | 内推|南加州地区 电路/电子/半导体类全职@qualcomm

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组内招人,有兴趣的请发送简历至qcdtechrefer@gmail.com。合适的简历会直接发给manager。工作需要每周至少4天on-site。

Job Details

·         Job Posting Title

Timing and Technology Engineer

·         Minimum Qualifications
.--
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field..google  и
.--
·         Job Description

As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets.

Responsibilities:

·         The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).
. From 1point 3acres bbs
·         You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.

·         Responsible for Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.. ----

·         You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in class timing ECO tools . Work on timing sign off specification for different projects and support timing sign off for complex SOC’s.  Hands on contribution for STA timing sign off.

·         A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow.  Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa,  RedHawk/SeaHawk/Voltus  is a plus.

·         You should have good execution knowledge.

·         Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production.

·         You should have good programming skills Python, Perl, TCL, Unix shell , C/C++.

·         ML modeling experience is a plus

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老哥,这是什么产品线的
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 楼主| zjushuishui 2024-3-29 01:52:03 来自APP | 显示全部楼层
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微信用户_1yde9 发表于 2024-03-27 18:26:47
老哥,这是什么产品线的
我们和不同的产品线都有合作。
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Lv17 2024-4-1 13:55:39 | 显示全部楼层
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简历已经发了,谢谢大佬
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Oryvendor 2024-4-21 08:17:52 来自APP | 显示全部楼层
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简历已发,谢谢大佬🙏🙏
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