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ASIC Design and Verification Engineer, Video Codec (Video Architecture) - 2021 Start
Responsibilities:
- Understand algorithm and architecture and design micro-architecture for hardware blocks
- Implement and verify hardware blocks using Verilog, SystemVerilog, or High-Level Synthesis tools
- Design and implement system control software and drivers for hardware accelerators
- Collaborate with hardware architects and verifications engineers for the successful delivery of hardware IPs
Qualifications
Required Qualifications:
- Currently pursuing a Bachelor's degree or above in Computer Science/Electrical Engineering, or equivalent fields, and will graduate during December 2020 - September 2021
- Solid experience in micro-architecture design, datapath pipeline design and optimization, and module-level design and verification
- Strong knowledge in SystemVerilog and solid experience with EDA tools (VCS, NCSim, Design Compiler, Genus, Verdi, Indago, Vivado, etc.)
- Experience in industry-standard buses (AXI, AHB, etc.)
- Collaborative mindset, with solid written and verbal communication skills
Preferred Qualifications:
- Knowledge of video codecs (AVC, HEVC, AV1, VP9, etc.) and experience in video codec design
- Experience in C/C++ development and debugging
- Experience in design verification, SystemVerilog assertions, checkers, formal verification, etc.
- Experience in DFT, low-power design, DDR, PCIe, embedded processor, and FPGA flow, etc.
- Experience in SW, FW, and device driver development |
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