NXP Wi-Fi Baseband 招NCG (2022年夏天毕业）

组里要招几个今年夏天左右毕业的NCG, Base在南湾 North San Jose，组内大多是华人，气氛非常好，老板很和蔼。平时工作大多可以用中文交流（应该是个加分项吧）
有兴趣的可以发我resume到

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岗位是硬件Digital Design 方向

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Job Summary:

Looking for a motivated DSP ASIC Design Engineer to work on design and verification in 802.11 wireless communications IPs for NXP Semiconductor wireless network products.
As a member in our Wi-Fi Connectivity Digital Design team, the candidate will be responsible for the design and verification of our IPs. Duties include but not limited to the following areas:
Block level micro-architecture design, RTL coding, verification, and documentation
Area/power optimization, and design trade-off analysis
Verification environment development and chip level verification planning and execution
Block and chip level synthesis, timing closure and formal verification
Chip bring-up and validation support
The candidate will work closely with the DSP systems engineers to understand the DSP systems design specifications of the assigned IP, and to work with the technical leads and other design engineers on the micro-architecture and interface requirements, and to work independently to design and verify the IP.

. 1point 3 acresKey Challenges:
Working on building wireless communication systems IPs requires a strong understanding of the protocol, the system specifications, micro-architecture, area and power tradeoff, front end design and back end design, silicon validation, and system level issue debugging. In addition, the Digital Design Engineer also will have the opportunity to expose to working knowledges in RF and Analog IPs, for example antennas, low noise amplifiers, mixers, low pass filters, power amplifiers, ADC, DAC, PLL, etc.
The work can be a challenge as there are so many things to learn in such a wide area of domains that it may takes years of practice to become an expert in this field. It not only requires learning many domain knowledges, various basic tools, and many hands on experience in design, verification, and mastering the ASIC flows, it also needs strong analytic capability and perseverance to strive in all kind of issues handling.

Cross functional aspects:
Working in the chip industry like NXP will expose you to experts in hardware, firmware, software, and the DSP communications and systems. The position will require interfacing with DSP systems experts, RF engineers, MAC engineers, SoC design engineers, Design Verification Engineers, firmware and software engineers, and hardware engineers.
The position requires participations in all stages of WiFi systems development, from the design specification, the RTL design and verification in block level, verification in SoC level, synthesis and timing closure, tapeout, silicon validation, and customer issue debugging support. You will have the opportunity to interact with different domain experts and to gain experiences and to excel from these interactions and learning.
. Χ
Job Qualifications:
The candidate must possess a Master of Science in Electrical Engineering or Computer Engineering
Up to 2 years work experience, including internships
Additional qualifications include:
Course works in VLSI and Digital Designs
Understanding ASIC design flow
Experience in micro-architecture design, RTL coding, and functional verification
Good understanding of synchronous/asynchronous design, and timing requirements for complex IP modules
Experience in Verilog HDL and Verilog design tools (Synopsys VCS, Verdi or similar) is required
Working knowledge of binary number format and its operation is required
Good understanding of DSP and Wireless Communication Systems/Algorithms is a plus
Experience in system Verilog is a plus
Strong verbal and written communications including the ability to write design documentation and verification plans
Familiarity with following common digital design tools is very helpful:
Verilog design tools (Synopsys VCS, Verdi or similar)
Synthesis tools (Synopsys Design Compiler)
Lint, CDC tools (Synopsys Spyglass or similar)
Static Timing Analysis tools (Synopsys PrimeTime)
Power estimation tools (Synopsys PTPX, Spyglass, Cadence Joule or similar)
Hardware validation tool (Palladium, FPGA etc.)
Handy with common scripts (shell, Perl etc.)
Handy with laboratory debug tools on chip support (Logic Analyzer, Oscilloscope)

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邮件已发，感谢楼主！ 邮箱是 qing***li@berkeley.edu

感谢楼主内推！

LZ 郵件已發 chon*******y@gmail.com

已发送邮件，感谢！

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