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我们组隶属soc dv, 做的是ip-level verification. 组里在扩招，整个org也在扩招，manager们多次强调特殊时期尤其不能放慢招聘的脚步。 new grad和有工作经验的都欢迎，能今年入职最好，明年入职的也考虑。location：Cupertino&Austin， no export license required感兴趣的请把简历发至：，符合条件的我会直接给manager。
job description可以参考：https://jobs.apple.com/en-us/det ... engineer?team=HRDWR
Key Qualifications
Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
Solid verification skills in problem solving, constrained random testing, and debugging
Experience defining coverage space and writing coverage model a plus. 1point 3acres
Experience with SystemVerilog Assertion (SVA) a plus
Team player with excellent communication skills and the desire to take on diverse challenges
Experience writing scripts in languages such as Perl or Python
Expertise in HVL and HDL (SystemVerilog, Verilog)
Advanced knowledge of HVL methodology (UVM/OVM)
Description
Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology. Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.. Waral dи,
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