2020高通memory 系统 微架构/VLSI/FW方向招人了，多个职位，直接给manager！强推！！

EE/CE的同学看过来！

前年和去年面试并强推了地里的同学最后成功入职，今年我又来了：）

地点都是San Diego。

组里职位不止一个，

1. VLSI design，做的是high speed memory system components （比如system cache，Memory controller，system NOC），会和SOC里的很多block打交道，也会有很多做micro-architecture的日常，对于VLSI track的同学来说，是一个非常好的机会！不要错过！

主要prefer new grad，new grad的背景要求：

GPA > 3.5，这是最低标准，低于这个标准简历基本就不看了，除非VLSI和architecture背景特别好可以特殊考虑。

强力VLSI背景/computer architecture背景是必须。

最好是已经毕业的。

老板很信任我，这个职位基本上就在地里找简历了，前年和去年都是地里直接去的。

简历请发送到：fengding AT qti dot qualcomm dot com， 注明是VLSI design

2. memory system firmware engineer，但这个职位不同于传统的firmware，基本上是system engineer，属于SW/HW co-design，需要对VLSI有很好的背景，对computer architecture较高要求，因为需要从system角度给软件和硬件分工做出规划，给designer做出反馈。

以后的职业发展就是往architect方向走，现在硬件设计领域的architect很多都是从firmware做上去的，因为做架构师需要对硬件，OS，firmware都要有很深刻的理解。

new grad背景要求：
VLSI背景要有
computer architecture背要有
C programming最好要懂一些
最好是已经毕业的

简历请发送到：fengding AT qti dot qualcomm dot com，注明memory system firmware engineer

3. 嵌入式软件的实习

这个职位是高通旁边的一个明星初创公司，做高速图像处理的FPGA，lead是高通SOC明星组出来的大牛，SOC方面非常厉害，做过骁龙旗舰SOC的功耗架构总设计，这个实习职位能得到这位高通大牛手把手辅导，对以后的职业发展是很好的，强烈推荐。

new grad 背景要求：
需要懂嵌入式软件，CE或者EE都可以，需要C programming，最好懂verilog，需要跟硬件和软件都打交道，会经历从硬件架构到软件架构的从头到尾垂直化的熏陶，以后往architecture方向或者嵌入式软件职业规划都是很好的选择
主动好学，乐于explore（虽然听起来很虚，但是很重要，因为东西很多，需要主观能动性去学习）

简历请发送到：fengding AT qti dot qualcomm dot com，注明嵌入式软件



.1point3acres

附： 1. VLSI design职位的description
SoC Memory System Microarchitecture/RTL Engineer (Job Family: HW Engineer)

Qualcomm is the largest fabless design company in the world, providing hardware, software and related services to nearly every mobile device maker and operator in the global wireless marketplace. A state-of-the-art high performance, low power memory system is at the heart of Qualcomms multi-tier mobile SOC roadmap. The memory system team is hiring talented engineers for architecture and microarchitecture development for low power mobile devices.   

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.  

MQ
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.

PQ
2+ years of RTL development experience including:
Experience with high-performance, low power micro-architecture concepts
Experience in Verilog and experience using simulator and waveform debugging tools.
Experience in logic design principles with timing, area and power implications.
Experience with scripting languages like Perl/Python/Java As an RTL engineer you will own or participate in microarchitecture development, RTL development, low power refinements, performance exploration, and meeting area and timing goals. Validation: support testbench development and simulation for functional and performance verification. Performance: explore high performance strategies and validate that the RTL design meets targeted performance. Design delivery: work with a cross-functional engineering team to implement and validate the physical design on timing, area, reliability, testability and power.

又花了40大米，再来内推板发几个帖子，我怕是都要降等级了
.google  и
其实这个版对于非CS方向的内推，多半是没有任何bonus而且自己需要花精力义务帮忙的，建议对于非CS方向的内推取消货币限制。

想当初这个内推板也算是我发起的吧，希望小k能考虑下：）

感谢楼主！
简历已发，h***u@ucdavis.edu，如果现在还可以的话，希望大佬帮忙内推一下

感谢楼主提供非CS内推

请问楼主其他部门的实习可以内推吗？

感谢楼主，简历已发 mingz*****@ucsb.edu

感谢楼主！！已发送简历：s*****yu@outlook.com

感谢楼主，简历已发 jzc6***@gmail.com

感谢楼主！wuyic***@umich.edu

多谢lz。求问可以帮忙内推AI/ML/DL方向的职位嘛？