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本帖最后由 billyuxiang1225 于 2019-12-11 07:13 编辑
一些之前ASIC DV onsite时候经常被问到的面试题, 也算回馈一下，跪求一些大米。
都是一些基础ABCDEFG大厂面经：
bit manipulation:
1. unset right most bit
2. power of 2
3. power of 4
4. turn on/off/toggle n-th bit
5. reverse bits.
constraints：
1. difference btw rand & randc
2. generate 10 unique number, later elements bigger than previous number
3. write MxN matrix, each 3x3 max is uniqle
4. what is soft constraint?
logic:
1. mux to implement: and, or, nand, nor, or
2. write ddf verilog with sync/async rst
3. rising edge detector
algorithm:
UVM Testbench/Systemverilog:
1. Draw UVM block diagram,: test,env, agent, sbd, where to insert mon & drv in your testbench, how to pass seq_item from mon to sbd?
2. How to get intf from DUT to mon/drv
3. implement timeout code
4. deep copy vs shadow copy?
5. is array pass by reference/value in task? how about object?6. what is functional & code coverage? if there is a hole in coverage, how to fix?
7. when to RTL sign-off?
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匿名用户-RLFEN
2019-12-12 08:13:32
匿名用户-RLFEN
2019-12-11 07:04:51
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