ScaleFlux 新融资，软硬各组都招人

ScaleFlux是一家做server storage的start-up，公司主体是一家硬件公司，所以设计到的软件都是偏底层Kernel, firmware之类的，公司整体氛围属于比较拼搏的阶段，如果说能力强上手快的话，能学到不少东西的。简历投到 jinchao.lyu@scaleflux.com，一定要写明是投哪个职位，有内推的会回信的

以下四个组招人：

软件组

System Software Engineer

We are looking for all level System Engineers to join our rapidly growing engineering team focusing on breakthrough cloud and data center infrastructure solutions involving both storage and computing systems. The core technology needed for this role includes computational storage system management software for enterprise-class applications ranging from big data processing, to database storage layers and infrastructures.
The ideal candidate for this role shares our passion for creating innovative technologies, and thrives in a highly dynamic, fast-paced, results-driven environment. We are looking for highly talented, passionate, and versatile engineers that can create the next generation enterprise data center solutions.
Location
•        San Jose, California

Responsibilities
•        Design and develop portable and scalable SDK platform for new generation computational storage chips/devices
•        Collaborate with architect and hardware engineers to deliver high performance computational storage system
•        Design and implement computation subsystem in a cutting edge computational SSD which integrated rich computation functions and enterprise level storage controller
•        Design and deploy benchmarks on big storage and database systems. Analyze and improve the efficiency, scalability, and stability with various system resources.

Qualifications
•        BS/MS Degree, majoring in Computer Science, Computer Engineering, Electrical Engineering or related working experiences
•        Strong experience in C/C++ development is required. Scripting experience in Python/Shell is highly desirable
•        Strong analytical and problem solving skills
•        Familiar with modern software development methodologies and principles
.. •        Experience with general purpose software library/API development is a big plus
•        Linux driver/storage stack experience and knowledge of NVMe is preferred
•        Demonstrated ability to work as a team player, as part of a local and globally distributed team
•        Highly adaptive to new work environment and eager to learn new technologies

招new grad，但是必须对C/C++有熟练掌握

Linux Software Engineer

Qualifications
•        Strong experience in C/C++ development is required. Scripting experience in Python/Shell is highly desirable
•        Familar with Linux kernel and have troubleshooting ability in Linux Kernel
• Have knowledge of File System and Block FTL is a big plus
• Have knowledge of local storage software stack is preferred
•        Highly adaptive to new work environment and eager to learn new technologies


不完全排斥new grad，但是如果对new grad面试要求可能会比较高，对自己有信心就投吧






硬件组

Hardware Engineer – Senior Design Verification Engineer
Location: San Jose, California
Responsibilities:

• Work closely with the design team to review and understand specifications / architectures / micro-architectures
• Define test plans
• Develop block level and chip level verification environments
• Produce functional / code coverage metrics
• Run regression and debug / triage failures in simulation environment
• Validate features and work with software teams to debug issues in the lab
  

Requirements:

• BSEE with 7+ years or MSEE with 5+ years experiences
• Advanced knowledge of standard ASIC/FPGA verification flows including simulation, testbench development, and post silicon bring-up and validation
• Excellent knowledge of System Verilog and Verilog
• Experience in developing test benches using the OVM, VMM or UVM methodology
• Good knowledge with C/C++
• Experience with either Perl or Python scripts
• Knowledge of industry high speed interface standard protocols (PCI Express, DDR, NAND Flash etc.) strongly desired
• Experience in computer storage and networking is desired
• Should be a team player with excellent communication skills and the desire to take on diverse challenges
  

这个职位不招new grad，就不要乱投了




Hardware Engineer – Emulation Engineer
Location: San Jose, California
Responsibilities:

• Support emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, Accelerated UVM Testbenches)
• Port ASIC/IP RTL to emulation platform and automate design compile environment
• Bring up SoC on emulation, root causing SoC/Processor test fails and emulator environment issues
• Assist debug of failures by providing instrumented model ( Waveform Dumps, in circuit debug) and interfacing with stakeholder
• Setup regression and debug / triage failures on emulation platform
• Collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams.
• Work with leading emulation vendors to debug issues
  

Requirements:

• BSEE with 7+ years or MSEE with 5+ years experiences
• Advanced knowledge of standard ASIC/FPGA verification flows including simulation, emulation, and post silicon bring-up and validation
• Excellent knowledge of System Verilog and Verilog
• Good knowledge with C/C++
• Experience with either Perl or Python scripts
• Experience with emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration (DPI and Transactor)
• Knowledge of industry high speed interface standard protocols (PCI Express, DDR, NAND Flash etc.) strongly desired
• Experience in computer storage or networking is desired
• Should be a team player with excellent communication skills and the desire to take on diverse challenges
  

这个职位不招new grad，就不要乱投了





Hardware Engineer – HW/ASIC Bring-up and Validation Engineer
Location: San Jose, California

Responsibilities:

• Work closely with the design team to review and understand specifications / architectures / micro-architectures
• Work closely with software team to define API and develop driver code
• Develop and execute test cases to validate new hardware features at module level and system level
• Build infrastructure for functional and performance validation, NAND characterization and manufacturing test
• Define test plans to cover ASIC design / drivers / NAND features.
• Run regression and debug / triage failures in validation environment and reproduce issues in simulation environment.
  

Requirements:

• BSEE with 3+ years or MSEE with 1+ years experiences
• Good knowledge of standard ASIC/FPGA design/verification/post silicon validation flows
• Experience with C/C++ and Python scripts
• Knowledge of industry high speed interface standard protocols (PCI Express, DDR, NAND Flash etc.) strongly desired
• Experience in computer storage and networking is desired
• Should be a team player with excellent communication skills and the desire to take on diverse challenges
  

RTL Design Engineer
Location: San Jose, California
Responsibilities:       

• ASIC/FPGA micro-architectures and implementation for SSD controller
• Design and simulate using industry standard EDA tools
• Lab bring up and debug
• Working with software team and/or customers to trouble shooting, debug, and tune system performance
  

Requirements:       

• Minimum B.S. Electrical Engineering or Computer Engineering, M.S. degree preferred
• 3 or more years proven experience in ASIC/FPGA design from concept definition to volume production
• Good coding skill of Verilog HDL
• Good knowledge of C or Python programming
• Demonstrated ability to resolve customer issues and deliver timely results
• Strong organizational and communication skills
• Familiar with DMA engine/controller or DPS engine design is a plus.
  

帮超哥顶一顶