南加半导体公司Indie Semi内推(Application engineer)

南加半导体公司Indie Semiconductor招Application engineer/Design Validation and Test engineer, 接受new graduate；
职位主要为，power management芯片实验测试以及芯片自动化测试/Board level电路设计，有power electronics的背景/有hands on experience的优先；

Job Summary:
• Validate ICs functionality in the lab against design and application requirements. Tasks includes test plan and procedure generation, initial chip bring up, full IP and chip level validation and characterization over process and temperature and debug analysis while product is in development stage.
• Define and develop the test setups with reasonable tradeoffs between accuracy, measurement time, and cost.
• Develop automation software for the tests using LabView or Python preferably.
• Design hardware fixtures, e.g. a PCB, as a part of the test setup if no off-the-shelf solution is available.
• Collect, consolidate and analyze test data for review with the design and quality teams.
• Participate to board and chip design reviews to make sure all the parameters can be tested. Help implement design features for testing and automation purposes.

提供内推，直接递给老板，简历发至：

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公司网站：www.indiesemi.com
公司地点：Aliso Viejo, Orange County, CA，非常宜居


补充内容 (2021-1-6 00:49):
Indie semiconductor相同职位目前有新的opening (2021年的opening)，简历可以发送至：xich19@gmail.com

简历已发！谢谢 vicki****@gmail.com

简历已发，yingh***@gmail.com， 感谢！

简历已发！Kk*****7@gwu.edu 谢谢！

感谢楼主! 公司好棒！我的邮箱是tmjiang8152@gmail.com，简历和一些背景介绍已发，再次感谢！

Indie semiconductor相同职位目前有新的opening (2021年的opening)，简历可以发送至：xich19@gmail.com

We are hiring Design Validation and Test (DVT) engineer , any level.
Work Location:
Aliso Viejo, CA/Austin, TX
Requirements
MS degree in Electrical and/or Computer Engineering
Have a solid foundation on basic circuit and demonstrated good understanding on basic analog circuits on areas like transistors, Op Amp, ADC, DAC, oscillator and clock. Ethernet, PCIe, Serdes knowledge is a definitive plus as indie.
Proficient at using various bench test bench equipment such as DMM, power supply, oscilloscope, spectrum analyzer, signal generator and VNA
Hands on capability to design and implement EDVT characterization tests with solid understanding of hardware design and manufacturing test parameters. Familiar with concepts such as spec compliance matrix.
Enjoy debugging as well as inventing more efficient ways to test indie’s ICs
Comfortable with MCU based systems and FW development tool chain.
Hands on capability to develop and implement test scripts using C, C++, LabView and Python programming.
Be systematic and very well organized, excellent communication skills as we do have offices in UK, Austin and California with FAE presence in Asia.