NXP半导体招Sr. DFT Design Engineer

NXP Semiconductor在上海浦东招Sr. DFT Design Engineer。hiring manager直接招人，请发简历到 nxp_referral AT mail DOT com


About the Position:
​As a member of a Shanghai wireless Design For Test (DFT) team, the candidate will work with DFT Lead (US base) and SOC team to design, develop BSCAN, MBIST and perform scan/edt insertion as well as pattern generation for various mixed-signals Chips.
​The member will also need design customized DFT module and develop the verification plan for DFT modules.
​Responsibilities:
​Tessent MBIST flow implementation/automation
​Scan/EDT insertion and ATPG with Mentor tools
​Verification of DFT Logic and analysis of fault coverage
​Timing analysis for DFT Modes
​ATE pattern delivery and bring-up
​Travelling for ATE bring-up (to US/Taiwan site) may needed but not mandatory
​Minimum Qualifications:
​Candidate MUST be MS degree or above in CS/EE or related technical field(s)
​Knowledge of Logic design & Static timing analysis
​Knowledge of Verilog, SV and any scripting language (perl, etc)
​1-3 years DFT industry experience
​Preferred Qualifications:
​3+ years (including internships) excellent Design, Development and ATE debug experience in MBIST, SCAN/ATPG with Tessent flow
​Good verbal and written communication skills in English
​Good design automation skills (Perl scripting etc)