【Moffett AI】AI 芯片初创公司极速强推, 可办身份

Moffett AI(墨芯人工智能) 公司内推，请发送简历至:

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or changxu.zhang@moffett.ai
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公司介绍:Moffett AI (moffettai.com) is pioneering in the next generation AI computing platform – sparse neural network processor. We build software and hardware systems specifically designed for sparse neural networks. Our AI computing platform is orders faster than existing GPU.

Moffett has recently closed its Series A financing and has received funding from prominent investors including Zhen Fund, Keytone Ventures, Inspur, Co-Stone Venture Capital, Greater Bay Area Homeland Development Fund.

Moffett cultivates a tight-knit team of smart, critical thinkers who care about their work and their colleagues. Our recruiting team is always on the lookout for supportive, down-to-earth, pioneering, and efficient candidates to grow our team's talent and enrich our culture. We offer a wide range of benefits, sponsorship for work visa and PR, competitive compensation, and substantial equity. We offer the right candidates room for growth in the technical fields and significant upward mobility in the organization.

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职位信息：

ROLE: ASIC Micro-architecture and Design Engineer
LOCATION: Los Altos, CA, USA
RESPONSIBILITIES:
·       Work with software and hardware engineering groups to design AI accelerator and SoC
·       Write detail specifications and define micro-architecture of the design
·       Implement high performance design using high-quality RTL coding techniques
·       Work with performance modeling/analysis team to enhance the performance
·       Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug
·       Work with the physical design team in aiding the implementation of the functional blocks
·       Work with multiple design groups to shape future design
·       Support the post silicon team to bring up silicon in the lab
·       Work with the software team to ensure product meets customer use cases
REQUIREMENTS:
·       BS/MS in Electronics Engineering with minimum of 3 years of RTL design experiences
·       Strong Verilog/SystemVerilog RTL coding skill
·       Experience in Micro Architecture/Resoruce tradeoff, SoC Integration, CDC, LINT
·       Experience with performing synthesis, timing analysis/timing closure, formal verification/LEC, DFT Design expertise
·       Hands on experience in AI chip design is a good plus
·       Knowledge with CPU/GPU/DSP/AI Accelerator Architecture Design
·       Familiarity with revision control concepts and tools (e.g. GIT)
BENEFITS:
·       401(k)
·       Dental insurance
·       Health insurance
·       Paid time off
·       Vision insurance
·       Life insurance
·      Free onsite lunch
====================================================

ROLE: AI Chip SoC Architect
LOCATION: Los Altos, CA, USA

RESPONSIBILITIES:
·       Responsible for SoC system functions and feasibility analysis of AI chips
·       Responsible for AI chip software and hardware function partition and SoC system architecture spec
·       Responsible for the detailed design of AI SoC chip including address space partition, chip interface and timing
·       Develop system emulators through languages such as C++/SystemC/Python and evaluate the performance of the AI SoC chip system, and propose design improvement
·       Write up architecture and microarchitecture documents and collaborate with RTL design and verification engineers
·       Work closely with other architects/hardware and software engineers for implementation, integration, and test plan development and execution
REQUIREMENTS:
·       Possess a Master's, PhD in EE/CS/CE or more than 6 years of relevant professional experience with successful complex chip tape-out experience
·       Experience in designing complex SoC systems such as CPU/GPU/AI chips
·       Experience with SoC bus (AXI/APB), NoC, video codec, CPU, GPU, host interface (PCIe) and memory technology (DDR)
·       Experience with VLSI design and verification, especially in power optimization methodologies
·       Strong working knowledge of ASIC design flow from RTL design to backend implementation
·       C/C++, Python scripting and Verilog design experience
·       Excellent written and oral communication, excellent organizational skills and high self-motivation
BENEFITS:
·       401(k)
·       Dental insurance
·       Health insurance
·       Paid time off
·       Vision insurance
·       Life insurance
·       Free onsite lunch
======================================================
ROLE: AI Chip SoC Architect
LOCATION: Los Altos, CA, USA
RESPONSIBILITIES:
·       Responsible for SoC system functions and feasibility analysis of AI chips
·       Responsible for AI chip software and hardware function partition and SoC system architecture spec
. ----·       Responsible for the detailed design of AI SoC chip including address space partition, chip interface and timing
·       Develop system emulators through languages such as C++/SystemC/Python and evaluate the performance of the AI SoC chip system, and propose design improvement
·       Write up architecture and microarchitecture documents and collaborate with RTL design and verification engineers
·       Work closely with other architects/hardware and software engineers for implementation, integration, and test plan development and execution
REQUIREMENTS:
·       Possess a Master's, PhD in EE/CS/CE or more than 6 years of relevant professional experience with successful complex chip tape-out experience
·       Experience in designing complex SoC systems such as CPU/GPU/AI chips
·       Experience with SoC bus (AXI/APB), NoC, video codec, CPU, GPU, host interface (PCIe) and memory technology (DDR)
·       Experience with VLSI design and verification, especially in power optimization methodologies
·       Strong working knowledge of ASIC design flow from RTL design to backend implementation
·       C/C++, Python scripting and Verilog design experience
·       Excellent written and oral communication, excellent organizational skills and high self-motivation
BENEFITS:
·       401(k)
·       Dental insurance
·       Health insurance
·       Paid time off
·       Vision insurance
·       Life insurance
·       Free onsite lunch

======================================================

ROLE: Design Verification Engineer
LOCATION: Los Altos, CA, USA
JOB DESCRIPTION:
·       Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
·       Contribute significantly to verification infrastructure development
·       Development of System Verilog/UVM based on test plan from functional requirements
·       Maintain regression list and run regression tests to make sure the design works correctly.
REQUIREMENTS:
·       Master degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
·       Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
·       Should have worked on developing/implementing test plans at the chip-level for complex ASICs. • Fluent in System Verilog and scripting languages such as Python or Perl.
·       Must have intimate knowledge of UVM methodology. • Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
·       Knowledgeable about assertions and functional coverage
·       Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
·       Very good communication skills and ability and desire to work in a geographically diverse team environment.
BENEFITS:
·       401(k)
·       Dental insurance
·       Health insurance
·       Paid time off
·       Vision insurance
·       Life insurance
·       Free onsite lunch

需要内推请发送简历至:

. 1point3acres.com

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Unlock interview details and practice with AI
Curated Interview Questions from Top Companies

or changxu.zhang@moffett.ai
（在标题内标注[Moffett Referral]）


补充内容 (2022-06-08 09:14 +8:00):
另有软件岗位招聘

ROLE: Compiler Research
JOB DESCRIPTION:

·       Be responsible for the deployment and optimization of the deep learning model on the end / cloud.
·       Be responsible for the research and development of AI compiler tool chain related software, including deep learning model front-end, compiler, back-end operator implementation, high-performance optimization, etc;
. ----·       Build easy-to-use, stable and high-performance AI compiler software platform products.

REQUIREMENTS:
·       Master Python / C + + programming skills, have a solid programming foundation, good programming style and working habits;
·       Meet at least one of the following requirements:
a.     Relevant development experience in TVM / MLIR / XLA or self-developed AI compiler;
b.     Experience in developing open source compilers such as GCC, llvm and Open64;
c.      Experience in CUDA / OpenCL / assembly level optimization of complex algorithms (such as image and video processing, computer vision, etc.);
d.     Those who understand deep learning algorithms (such as CNN / RNN / LSTM, etc.);
e.     Familiar with at least one deep learning framework such as Caffe / tensorflow / mxnet / Python / onnx;
f.      Understand CPU or GPU architecture.
g.     Excellent written and oral communication skills.

ROLE: Sparse Computing Research Scientist
Operating Duty:

·       Be responsible for the research of frontier model compression algorithm (quantization, pruning, distillation and sparseness)
·       Be responsible for the implementation of advanced model compression algorithms
·       Participate in the design and implementation of model compression training platform
. ·       Assist in the application of model compression algorithm in specific fields (CV, voice)
·       Explore the next generation model acceleration algorithm

REQUIREMENTS:

·       1. Master degree or above in computer, electronics, communication or mathematics, doctor is preferred.

y***2@cornell.edu 简历已发，已加米，感谢楼主！

已发！顶一下！

收到内推了！感谢楼主！